Recent electronic apparatuses such as personal digital assistants (PDAs) and so on are equipped with devices requiring a power source voltage higher or lower than a battery voltage. A step-up, step-down or step-up/step-down type switching regulator is used to supply a proper power source voltage to such devices.
FIG. 1 is a circuit diagram showing a switching regulator 4r. The switching regulator 4r includes a control circuit 100r and an output circuit 102. The output circuit 102 includes a switching transistor M1, a synchronous rectifying transistor M2, an inductor L1 and an output capacitor C and has a topology of a step-down type switching regulator. The control circuit 100r switches the switching transistor M1 and the synchronous rectifying transistor M2 to stabilize an output voltage VOUT to a target value.
The control circuit 100r includes a bottom detection comparator 10, a driving circuit 20r, a peak current detector 50 and a zero current detector 60. A first voltage-dividing resistor R1 and a second voltage-dividing resistor R2 divide the output voltage VOUT to generate a feedback voltage VFB based on the output voltage VOUT. The bottom detection comparator 10 compares the feedback voltage VFB with a predetermined reference voltage VREF and generates an on signal SON asserted (for example, having a high level) when the feedback voltage VFB decreases to the reference voltage VREF.
The peak current detector 50 includes a current detector 52 and a peak current detection comparator 54 and generates an off signal SOFF asserted when current IM1 flowing into the switching transistor M1 reaches a predetermined peak current IPEAK.
In an on period of the switching transistor M1, a voltage VLX of a junction point (a switching terminal LX) of the switching transistor M1 and the synchronous rectifying transistor M2 is given by VDD−IM1×RON1. Where, RON1 denotes an on resistor of the switching transistor M1. The current detector 52 generates a detection voltage VIM1 depending on a voltage drop (IM1×RON1) of the switching transistor M1. The peak current detection comparator 54 compares the detection voltage VIM1 with a threshold voltage VPEAK corresponding to the peak current IPEAK and asserts the off signal SOFF (for example, having a high level) when the detection voltage VIM1 reaches the threshold voltage VPEAK, in other words, when the current IM1 reaches the predetermined peak current IPEAK.
The zero current detector 60 generates a zero current detection signal SZERO asserted when current IM2 flowing into the synchronous rectifying transistor M2 decreases to a near-zero threshold value IZERO. In an on period of the synchronous rectifying transistor M2, a voltage VLX of the switching terminal LX is given by VIM2=−RON2×Im2. Where, RON2 denotes an on resistor of the synchronous rectifying transistor M2. The zero current detector 60 includes a comparator to compare the voltage VLX of the switching terminal LX with a predetermined threshold voltage VZERO.
The driving circuit 20r includes a control logic part 22r and a pre-driver 24. The control logic part 22r receives the on signal SON, the off signal SOFF and the zero current detection signal SZERO and generates a control signal to direct turning-on/off of the switching transistor M1 and the synchronous rectifying transistor M2. The pre-driver 24 controls the switching transistor M1 and the synchronous rectifying transistor M2 based on the control signal generated by the control logic part 22r. 
When the on signal SON is asserted, the driving circuit 20r turns on the switching transistor M1 and turns off the synchronous rectifying transistor M2. Subsequently, when the off signal SOFF is asserted, the driving circuit 20r turns off the switching transistor M1 and turns on the synchronous rectifying transistor M2. Subsequently, when the zero current detection signal SZERO is asserted, the driving circuit 20r turns off both of the switching transistor Ml and the synchronous rectifying transistor M2.
FIG. 2 is an operation waveform diagram of the switching regulator 4r of FIG. 1. The bottom detection comparator 10 of FIG. 1 is configured to have a high response speed and a very small delay. At time t1, when the feedback voltage VFB decreases to the reference voltage VREF, the on signal SON is immediately asserted and the switching transistor M1 is turned on.
When the switching transistor M1 is turned on, the voltage VLX of the switching terminal LX rises to the proximity of an input voltage VDD. In addition, as coil current LCOIL increases, i.e., as the current LM1 of the switching transistor M1 increases, a voltage drop of the switching transistor M1 increases and the voltage VLX of the switching terminal LX is being lowered.
At time t2, the voltage drop of the switching transistor M1 reaches the threshold value VPEAK. In other words, the voltage VLX of the switching terminal LX decreases to VDD−VPEAK.
The peak current detector 50 has response delays, specifically, a delay in the current detector 52 and a delay in the peak current detection comparator 54. Due to the sum τD of these delays, the off signal SOFF is asserted at time t3 after lapse of the delay time τD from time t2. At time t3, the switching transistor M1 is turned off and the synchronous rectifying transistor M2 is turned on. At time t4, when current flowing into the synchronous rectifying transistor M2 decreases to the near-zero threshold value IZERO, both of the switching transistor M1 and the synchronous rectifying transistor M2 are turned off.
In the switching regulator 4r of FIG. 1, for the delay time τD between time t2 and time t3, the coil current ICOIL, i.e., the current IM1 of the switching transistor M1, continues to increase and reaches IPEAK′. In other words, in order to set the actual peak current IPEAK′ of the coil current ICOIL to a desired target value, there is a need to determine the peak current IPEAK, i.e., a threshold voltage VPEAK, in consideration of a length of the delay time τD and a slope of the coil current ICOIL.
For example, assuming that VDD=3.7V, VOUT=1.7V, inductance of the inductor L1 is 2.2 μH, IPEAK′=100 mA, and τD=60 ns, the desired IPEAK is approximately 45.45 mA. Assuming that RON1=0.2Ω, a voltage drop of the switching transistor M1 is 9.09 mV=0.2Ω×45.45 mA. That is, the peak current detector 50 needs to compare the voltage drop, which is likely to be a few millivolts (mV), with the threshold voltage VPEAK. However, in actuality, it is difficult to compare the voltage drop in millivolts (mV) with the threshold voltage, which may result in erroneous detection.